1. Field of the Invention
The present invention relates to the structure of a field effect thin film transistor (hereinafter referred to as TFT), and more specifically to the structure of a TFT using amorphous silicon as a semiconductor layer in which the resistance at source and drain electrodes is small and in which leakage current by response of minority carriers is small in the OFF state.
2. Description of the Prior Art
Conventional TFT structure is described below. FIGS. 1 through 3 shown cross sections of conventional TFT structure, in which a gate electrode 20, 21, 22 is formed on an insulating substrate 10, 11, 12 and gate insulating film 30, 31, 32 is formed to cover the gate electrode 20, 21, 22. For the TFT structure shown in FIG. 1, a non-doped amorphous silicon film 40 is then formed over the entire surface of the gate insulating film 30. For the TFT shown in FIG. 2, a non-doped amorphous silicon film 41 is formed on the central portion of the gate insulating film 31. Then, metal films are formed thereon over the respective end portions of the gate electrode 20, 21 to define a source electrode 50, 51 and a drain electrode 60, 61. For the TFT shown in FIG. 3, n+ amorphous silicon film 72, 82 is formed each on both end portions of the gate insulating film 32. Then, source and drain electrodes 52, 62 are formed on the n+ amorphous silicon film 72, 82, and finally a non-doped amorphous silicon film 42 is formed in the center on the gate insulating film 32 and on the electrodes 52, 62.
In a TFT with the structure shown in FIG. 1, when the TFT is ON, a current path exists not only on the surface of the non-doped amorphous silicon film 40 to the gate electrode 20 side but in other parts of the amorphous silicon film 40, as shown in FIG. 4. That is, drain current cannot be fixed solely by the face resistance (channel resistance) Rch generated by the laminate layer on the surface 40a of the amorphous silicon film 40 to the gate electrode side, because of gate voltage applied between the gate electrode 20 and source electrode 50. Furthermore, the non-doped amorphous silicon film 40 of high resistance interposed between the source electrode 50 and the laminate layer on the surface 40a causes a resistance (contact resistance) Rco, resulting in a high resistance in an ON state. When the source and drain electrodes 50, 60 are made of metal material such as aluminum, they effect virtually ohmic contact with both electron and positive hole carriers. As a result, minority carriers are injected for response causing leakage current in an OFF state (low resistance in an OFF state). The leakage current can be prevented in an n-channel mode TFT in which n+ layer is interposed between the non-doped amorphous silicon film 40 and the source and drain electrodes 50, 60. In this case, it is necessary to selectively etch the non-doped and n+ amorphous silicon films. However, since these films have the same chemical property, they must be etched selectively by controlling the etching time so that parts of the films are etched away to the required thickness accurately. Meanwhile, the non-doped layer 40 must be made thin enough to obtain a TFT that has a high resistance in the OFF state, and therefore has no thickness allowance for etching. Accordingly, when a plurality of TFT's are formed over a wide area as required in an active matrix liquid crystal display unit, the thickness allowance of the non-doped layer 40 is not enough to cover fluctuation of the film thickness and etching rate. That is, selective etching is virtually impossible.
For the TFT with the structure shown in FIG. 2, the contact resistance Rco has no effect on the TFT characteristics when the non-doped amorphous silicon layer 41 is thick. When it is thin, however, a current path as shown by .circle.b in FIG. 5 occurs, giving a considerable effect to the TFT characteristics. Namely, fluctuation of the TFT characteristics results. In this case as well, the non-doped amorphous silicon layer 41 should be thin to obtain low resistance in the OFF state. If an n+ layer is interposed between the metal electrode 51 and the non-doped amorphous silicon layer 41 to prevent minority carrier injection, selective etching becomes necessary, though it is not possible for the same reason as that in the case of the TFT of FIG. 1.
In a TFT with the structure shown in FIG. 3, the non-doped amorphous silicon layer 42 is made in direct contact with the n+ amorphous silicon films 72, 82 on the gate insulating film 32, so that the contact resistance Rco does not influence the TFT characteristics any more. However, because of the direct contact between the non-doped amorphous silicon film 42 and the metallic source and drain electrodes 52, 62, minority carrier injection (response of positive holes) cannot be restrained by the n+ amorphous silicon layers 72, 82. The minority carrier injection can be prevented either by removing the metallic electrode 62 or by offsetting it to the extent that it does not overlap the non-doped amorphous silicon layer 42. With the latter option, it is necessary to selectively etch the non-doped amorphous silicon layer 42 and the n+ amorphous silicon layer 82. Thus, even with the structure shown in FIG. 3, it is virtually impossible to obtain a TFT with the required characteristics.